This past week I attended the Chips National Advanced Packaging Manufacturing Program (NAPMP) Proposers’ Day where the US government described funding opportunities for companies that can advance the state of the art for semiconductor packaging. Under the Chips Act, the government is making $1.55 billion available. Awards range up to $150 million, indicating it will disburse at least 10 awards. Even if you don’t consider your organization to have packaging expertise, you may find an opportunity for it to contribute—and get a grant. However, you must act fast. Ten-page concept papers are due December 20. I’m available to help you apply.
A Badass NOFO
The NAPMP notice of funding opportunity (NOFO) seeks proposals in five areas:
- Equipment, tools, processes, and process integration
- Power delivery and thermal management
- Connector technology, including photonics and radio frequency (RF)
- Chiplets ecosystem
- Codesign/electronic design automation (EDA).
A proposal can (perhaps should) address only a single area; in some cases, it need only tackle a single objective within the area. Ultimately, awardees with complementary efforts will collaborate on developing a complete packaging solution, but organizations can team up in the initial phase as well.
Chiplet Objectives
The NAPMP vision centers on chiplets, which is the area best aligned with my expertise and client base. Proposals must show how to employ a future bond pitch approaching 1µm (i.e., sub-10 µm). They should focus either on high-performance or low-power applications and address four objectives:
- Scale down—advances the state of the art to enable a simpler, cheaper, highly parallel die-to-die interface and smaller chiplets made possible by wire abundance. (This area’s leader assumes a far greater quantity of die-to-die connections will be available than in today’s chiplet-based designs. Winning proposers will focus on making this a reality.)
- Scale out—advances the state of the art to leverage scale-down and ultralarge packages to create systems of hundreds to thousands of chiplets (high-performance only).
- Ecosystem—advances the state of the art in modular design to cost-efficiently build and operate adaptable systems that leverage scale-down and scale-out.
- Technology demonstrators—integrate outputs from scale-down, scale-out, and ecosystem objectives into a system demonstrating suitability and utility of outputs for use by U.S. industry and research.
For the chiplet area, $300 million will be available, and award size will top out at about $75 million.
Who Is Interested?
At the event, I saw badges from Applied Materials, Cadence, HP, IBM, Kulicke & Soffa, Nvidia, PDF Solutions, QuickLogic, Synopsys, UCLA, and the University of Maryland. Companies on the attendee list include Alphawave, Altera, AMD, Analog Devices, Arm, Ayar Labs, Celestial AI, Cerebras, Eliyan, Global Foundries, Infinera, Intel, Micron, NXP, Qorvo, Samsung, SK Hynix, Tenstorrent, TI, TSMC, Wolfspeed, and Zero ASIC.
If your company isn’t on the list, it probably should be if it’s working on chiplets, interconnects, or other fields under the broad packaging umbrella. I’m available to work with you on a proposal, and I have the advantage of being local to NIST, the relevant government agency.