-
Tensordyne Napier Slashes Costs and Boosts Token Rates
The Tensordyne Napier NPU aims to beat Nvidia/Groq and Amazon/Cerebras at a fraction of the power, floor space, and cost, owing to logarithmic computing. continue reading
-
BWR Ep 14: Broadcom, Marvell, and Nvidia Earnings Plus New Tech
Byrne and Wheeler discuss recent developments in the tech industry, including AMD’s acquisition of MEXT, #NVIDIA’s impressive growth, Broadcom’s earnings, and innovative chip technologies like Tensordyne’s log-domain processing and Huawei’s Tau scaling. They analyze market trends, product launches, and strategic partnerships shaping the future of semiconductors and AI hardware. continue reading
-
Bolt Confounds Skeptics, Tapes Out Zeus GPU
Startup GPU maker Bolt Graphics is on track to deliver development kits to lead customers by the end of the year, having taped out its first chip last month. By the end of 2027, the company expects to begin shipping PCIe cards based on a production version of its Zeus GPU. This schedule represents a… continue reading
-
Matrix Multiplication Comes to x86
The x86 Ecosystem Advisory Group (EAG, better known as AMD and Intel) has defined the AI Compute Extensions (ACE) for the x86 architecture. The group frames these instructions as a palette, a term Intel coined for a specific configuration of its Advanced Matrix Extensions (AMX). Those AI-focused instructions and associated hardware first appeared in Sapphire… continue reading
-
Blowout AMD & Intel Earnings, Google TPUv8, Astera Scorpio-X, RISC-V New, and More: It’s BWR Ep 13.
This episode features an in-depth discussion on the latest developments in data center chips, AI accelerators, interconnect technologies, and RISC-V ecosystem growth. Experts analyze AMD and Intel earnings, Google TPU v8, Astera Labs’s Scorpio-X, and emerging startups, providing insights into market trends, technological innovations, and strategic shifts. continue reading
-
Google TPUv8: Early Specs and Performance Gains
Google has unveiled its eighth-generation AI accelerator, revealing a design similar to past designs but with greater per-socket throughput, faster networking, and new collective engines. Per-chip gains should improve cost per token and performance, particularly as large language models grow well beyond 1 trillion parameters. As with some previous generations, the new accelerator (NPU) has… continue reading
Popular
Sponsored Content and Plugs
- BWR 12: The Memory Episode
- Slash Server Costs Without Hardware or Software Changes
- Ceva Boosts NeuPro-M NPU Throughput and Efficiency
- MEXT Helps IT Leaders Find the Sweet Spot
- Chips Act Backs Chiplets
Other Sites You Might Like
Read More
Amazon AMD Arm auto Broadcom business Cerebras Ceva consumer CPU data center DPU DSP edge AI embedded FPGA Google GPU Groq Imagination industrial Intel Marvell MCU MediaTek Meta MEXT Microsoft MLPerf NPU (AI accelerator) Nvidia NXP OpenAI PC process tech Qualcomm RISC-V SambaNova Semidynamics SiFive smartphone software Tensordyne Tenstorrent Upscale