• Taalas Technology to Boost AMD AI Performance and Efficiency

    Han Solo frozen in Carbonite

    AMD has acquired Taalas, an AI-acceleration startup that hardwires models to achieve eight times the token rate of its nearest competitor while requiring a fraction of the power. Located in Toronto and founded by Tenstorrent cofounder Ljubisa Bajic, Taalas has demonstrated a chip implementing the Llama 3.1 8B model. AMD states that the company will… continue reading

  • Ain’t Too Proud: The AMD MI455X Story

    AMD MI455X chip with Cubist filter applied

    AMD has aligned its data-center GPU architecture with that of market leader Nvidia. However, AMD highlights the token-throughput and efficiency gains of the new MI455X over the previous-generation MI355X instead of touting how customers will find it easier to port their AI models to the GPU. Implementing the CDNA 5 architecture, the MI455X is the… continue reading

  • BWR 16: AMD AI Day, Nvidia Vera, Astera Taurus, Hot Chips Preview

    Thumbnail of BWR-16 teasing discussion of AMD's AI day and Nvidia Vera

    In Episode 16 of the Byrne-Wheeler Report, Joe and Bob discuss the latest developments in AI hardware, including disclosures at AMD’s Advancing AI day, NVIDIA Vera, and upcoming conferences Hot Chips and OCP APAC. They analyze new processor architectures, interconnect standards, and market implications for AI and data center computing. Click above to play the… continue reading

  • AMD Scales Epyc 9006 “Venice” to 256 Cores and 1 GB of L3 Cache

    AMD Epyc 9006 package and die

    AMD has revealed the first models of its sixth-generation Epyc product line, Venice. Based on the new Zen 6 and Zen 6c cores, the now-shipping processors offer two packaging options. Maximum core count increases from 192 in the previous Turin generation to 256. As before, the highest-frequency chips boost to 5 GHz. Across the board,… continue reading

  • NextSilicon Arbel Targets RISC-V Servers

    NextSilicon Arbel chip with exposed die

    NextSilicon, a startup focusing on processors for high-performance computing, is developing a server-class 64-core CPU chip called Arbel. A RISC-V design based on a core NextSilicon employed in its Maverick-2 data-flow compute accelerator, Arbel is due to ship in early 2028. A development chip is already in customers’ hands. The RISC-V architecture has been mooted… continue reading

  • Nvidia Vera’s High-Bandwidth Architecture Targets the Agentic-AI Era

    Nvidia Vera CPU chip with exposed die

    Nvidia is mounting a charm offensive for its Vera microprocessor, touting its sizable strengths in key areas and retconning it into a framework of how data-center processors have changed. If this framework is valid, the company is at least one generation ahead of other server-processor suppliers. At the same time, Nvidia claims that competing products… continue reading

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