Codasip has announced a RISC-V CPU targeting automobile electronics. Available for licensing now, the new L730 optionally integrates the Codasip Cheri security extensions and scalar RISC-V crypto instructions, and its functional-safety capabilities support ASIL D integrity.
Licensable designs (IP) can comply with safety standards, but Codasip goes further than mere compliance and obtains certifications. Priding itself in its safety expertise, the company’s staff includes engineers from automotive suppliers. The team expects the L730’s out-of-context certification to facilitate licensees obtaining their approvals, reducing time to market.
The 32-bit L730 core joins the company’s A730 and X730 designs in delivering midrange performance to SoC designers. The 64-bit A730 includes a memory management unit (MMU) to run Linux, suiting it to application-processing functions. To this design, the X730 adds Cheri, which helps bar inappropriate memory accesses. Codasip has donated the Cheri software development kit (SDK) to the Cheri Alliance and is pushing for the RISC-V community to adopt the technology.
Inside the Designers’ Studio
The 730-series cores are dual-issue, in-order CPUs and should deliver performance similar to an Arm Cortex-M7, M85, or R52. Designers can enhance performance through custom instructions, Codasip’s third differentiator alongside safety and security. The company’s designs are both configurable and customizable through the Codasip Studio development environment. It enables licensees to choose off-the-shelf options and to add new instructions defined in the CodAL C-like language. A code profiler helps the licensee identify hot spots benefiting from customization.
Similar to the Tensilica technology from Cadence for the proprietary Xtensa core, the Codasip tool also generates a compiler and verification environment alongside the customized CPU. Fellow RISC-V startup Semidynamics also supports configuration options and extensive design changes, but the latter entails manual work by the IP supplier. Synopsys may be Codasip’s closest competitor, offering a configuration and customization tool for its Arc CPU and cores compliant with safety standards.
Bottom Line
Designers can choose from a long list of RISC-V cores, and the architecture has consolidated the market for low-cost control CPUs. A plain RISC-V core could offer better performance, power, and area (PPA) than an Arm Cortex-M or Cortex-R CPU but wouldn’t be profitable given the proliferation of such cores. A RISC-V supplier must differentiate.
In most cases, chip designers bury RISC-V cores in their SoCs and don’t offer them to customers to program. However, the automobile industry is among the first to consider the instruction set for more than deeply embedded control use. Moreover, automobile OEMs and Tier-One suppliers have the resources to employ CPU customization to raise performance; they also demand functional safety and must secure car software from hacking.
Against this backdrop, the Codasip L730 offers designers a CPU that goes beyond trading Arm compatibility for better PPA. It provides a differentiated combination of safety, security, and customization for designers seeking midrange performance in a RISC-V core.