Year: 2025

  • Xsight Labs Develops 800 Gbps DPU That Hosts Linux

    Xsight Labs Develops 800 Gbps DPU That Hosts Linux

    Xsight Labs will soon sample the E1 DPU to complement its X2 switch. Although 800 Gbps capable, it runs packets through its 64-core Arm Neoverse cluster. The E1 promises a simple programming model, flexibility, and performance.

  • Arm Publishes Chiplet System Architecture Spec

    Arm Publishes Chiplet System Architecture Spec

    Arm has published the first Chiplet System Architecture (CSA) specification, aiming to accelerate Neoverse adoption. The CSA initiative allows customers to acquire pre-built CPU dies, simplifying complex chip designs. The CSA spec covers interfaces, management, and security, hurdles to widespread merchant chiplet deployment.

  • Marvell Structera Transcends CXL Memory Expansion

    Marvell Structera Transcends CXL Memory Expansion

    Marvell’s Structera CXL chips boost memory bandwidth and capacity. Structera A, a DPU with 16 Neoverse-V2 cores, accelerates workloads, while Structera X expands memory capacity and supports dual-host pooling. Sampling now, both accelerate encryption and compression to add security and increase effective memory capacity.

  • Intel Will Nix P-Cores and Fall Behind on Single-Thread Performance

    Intel Will Nix P-Cores and Fall Behind on Single-Thread Performance

    Intel will soon only employ only E-cores, a strategy consistent with the view that general-purpose processors’ role is feeding and managing AI accelerators. This will end in disaster for the company.

  • CES 2025 Roundup

    CES 2025 Roundup

    CES 2025 showcased processor technology, with a strong focus on AI. AMD unveiled the Strix Halo integrated graphics processor (APU), while Nvidia showed the more powerful GB10 APU in its Project Digits workstation. The roundup also covers key developments from embedded players like Alif, Ambarella, and Renesas.

  • Marvell Copackages Optics for Custom Silicon

    Marvell Copackages Optics for Custom Silicon

    Marvell’s custom silicon operation now offers copackaged optics (CPO). Enabling systems to connect fiber-optic networks directly to chips such as AI accelerators (NPUs) and network switches raises per-chip bandwidth and extends interchip connectivity distances. Few companies offer CPO. Broadcom, Marvell’s main custom-silicon rival, has developed a few Ethernet switches implementing the technology and, this past…

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