The Cadence ChipStack AI Super Agent automates chip development, boosting engineers’ productivity. Employing a large language model (LLM), the tool automates design and verification. It assists engineers by orchestrating design-flow steps and aiding verification. It’s available to early-access customers, and ten of them are already piloting it.
The new AI-based tool is Cadence’s first ChipStack product since its November acquisition of the ChipStack company, which had several AI tools, including the Mental Model Agent. That software captured a design’s intent by ingesting data such as RTL and specifications. From there, it could formulate a comprehensive spec, aiding both human engineers and the startup’s verification agents. The new super agent enhances this technology, linking it to Cadence’s other EDA tools.
Agents and Super Agents
We define an AI agent as a model (typically an LLM) that can use tools. It can invoke other software instead of simply generating a response. A super agent is a model that calls other AI agents, orchestrating them to achieve an objective.
Cadence hasn’t detailed the ChipStack AI Super Agent but indicates that it works with the customer’s preferred LLM. We therefore infer that it’s a combination of scripts and prompts. Because the mental model represents a design in a specific structure, the new tool mitigates the risk of LLM hallucinations and provides a consistent framework for downstream agents to plan and execute tasks.
A Virtual Organization
Cadence aims to automate design and verification, reducing the time and cost of achieving timing or power closure after a design change. In an all-human methodology, closure is a whole-team integration effort, which is too costly for incremental changes. With ChipStack, an individual engineer can kick off the process after a small change. The company describes the ChipStack Super Agent as a virtual organization, not a virtual engineer; it automates processes instead of replacing personnel.
Nevertheless, it does some engineering work. It develops test plans and writes code to implement them. It can employ Cadence’s EDA tools to execute the tests and evaluate results. We believe these steps can run autonomously, but most organizations will have a human in the loop. The ChipStack tool can then use the test results to debug RTL, or at least hint at where problems lie. In its press release, Cadence quotes Altera as reporting that the super agent reduces verification effort in “some areas” by 10 ×. Tenstorrent reports a fourfold verification-time reduction.
Bottom Line
A few years ago, the prevailing notion was that enterprises would train or fine-tune their models. By working with any LLM, ChipStack demonstrates that businesses will use models off the shelf, customizing only prompts and code scaffolds. Chip development is an interesting AI application. Although LLMs have been used to generate software, there are no high-profile examples of an LLM capable of generating RTL, such as Verilog. However, chip design is a lengthy process in an industry that values time to market. By accelerating the process instead of offloading it wholesale from human engineers, Cadence is initiating a new era in semiconductor development that should result in better-quality chips and shorter design times.