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Rivos Emerges from Stealth, Hints at RISC-V Plans

While announcing it has raised more than $250 million, heretofore-stealth startup Rivos disclosed it’s developing a 3 nm data-center processor combining RISC-V CPUs and a math engine. Unlike Untether’s at-memory SpeedAI240 (Boqueria), which also fits this high-level description, Rivos promises uniform access to standard DRAM and HBM. This being 2024, large language models (LLMs) are a target, but Rivos seeks to generally address data analysis. Its technology promises to be easy to program and debug, although details remain tightly held.

Central to this approach appears to be the use of a standard CPU architecture. Rivos has contributed to the RISC-V community, including by co-chartering the Rise project. The company’s three founders are CPU guys, including two that worked at P.A. Semi. While many data scientists work at a high level of abstraction, employing software such as Matlab and PyTorch, lower levels must be optimized for the underlying hardware. Simplifying the task of programming these layers can improve developers’ productivity and machines’ power efficiency.




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