To address AI accelerators’ need for a scalable interconnect, network-on-chip (NoC) specialist Arteris has added mesh-topology support to its licensable FlexNoC and Ncore designs (IP). Employing the company’s parameterizable IP, chip developers can configure the NoC from a few nodes to more than 1,000. They can also reuse a common building block throughout their design, getting to market sooner by reducing integration time. Arteris NoCs also include features such as dynamic frequency scaling, fault detection, and QoS.
Scalable-mesh demand has taken off because many AI accelerators (NPUs) rely on replicated logic, tiling independent processing elements (PEs) in a two-dimensional grid. Connecting an element to its north, south, east, and west neighbors is a straightforward point-to-point link. However, communication among all tiles and other function units such as DRAM controllers is much more complex. Moreover, chip developers with a product family spanning different-size NPUs must adapt the on-chip interconnect accordingly.
Laying the Groundwork
Having supplied the market with NoC IP for the past twenty years, Arteris has laid the groundwork to address this demand. The company pioneered scaling SoCs by enabling designers to connect function units to a local interconnect segment that link up through on-chip routers.
Arteris has adapted its technology to the regular mesh topology required by many NPUs. Each tile integrates a PE with an Arteris network interface unit (NIU) that connects it to the mesh’s north-south and east-west NoC highways. These include lanes for moving bulk data and for control functions. The company’s approach allows each tile to be identical, integrating the same PE and NIU logic. Scaling design requires only replicating more tiles in the 2D array, leaving the basic building block unchanged—no manual configuration of the NIU based on its location in the grid is needed. Interfaces to DRAM, PCIe, or the rest of an SoC can tie into the mesh along the periphery of the array.
For NPUs that manage memory with software, Arteris offers FlexNoC. For general-purpose computing, designers also employ tiling to connect CPUs. These processors usually require the NoC to maintain memory coherency, a capability Arteris offers with Ncore. An SoC integrating a variety of function units can employ both NoCs, such as Ncore for the CPU cluster, FlexNoC within the NPU, and another FlexNoc instance to link the CPUs, NPUs, and other units. Figure 1 depicts such a SoC, along with Magilem configuration registers for setting up the NoCs and a CodaCache last-level cache.
With an Arteris NoC, a designer can put tiles in different clock domains to manage power. By simply writing to a control register during runtime to halt a domain’s clock, an SoC controller can dynamically disable tiles to save power during light workloads. Designers also have the option to control voltage for further savings.
Bottom Line
Data movement is as essential to AI acceleration as processing. The leading NoC supplier, Arteris is well positioned to capitalize on demand for the mesh interconnect that ties together NPU processing elements. Adding mesh-topology support, it has extended the interconnect IP that it has already licensed to more than 200 customers and is the first independent company we’ve seen offer such a NoC.
Demonstrating the company’s success, Arteris already has many semiconductor customers targeting automotive and computing applications, two segments rapidly adopting AI processing. By its count, Arteris has more than five customers developing AI training chips, 20 targeting data-center inference, and 45 addressing edge and endpoint inference. Companies designing an NPU or other product employing a grid of replicated logic will find Arteris offers a flexible solution to tying together chip functions.