Processor icon MIPS is further reinventing itself, having replaced its eponymous CPU architecture with RISC-V. The company is focusing on “physical AI,” a term encompassing real-time processing, and MIPS will develop chips to complement its licensed designs (IP). To address physical AI, MIPS is creating an AI accelerator (NPU) and a new CPU. An FPGA-based evaluation board should arrive by the end of the year and reference silicon by the middle of 2026.
Targeting Physical AI
Real-time processing is at the heart of the physical AI concept and covers applications such as motor control, industrial networking, and battery management (e.g., monitoring state of charge). Compared with traditional computing, these applications emphasize determinism over throughput and are typically event driven. They’re common in automotive and industrial sectors, which also demand functional safety. Therefore, MIPS sees compliance with safety standards such as ASIL as another physical-AI cornerstone attribute.
A further attribute, a conspicuous part of the term physical AI, is AI. MIPS is developing an NPU, aiming to build an inference accelerator that scales from a few TOPS to thousands of TOPS. Initiating the project more recently than other edge-AI NPU developers, MIPS intends to support multimodal neural networks (e.g., those that verbalize image details instead of simply classifying image contents) and mixture-of-expert (MoE) models—an unlikely use case because MoE models are usually too large for edge applications. Called the S8200, the NPU will comprise four multithread RISC-V cores with AI coprocessors for matrix and vector operations.
RISC-V for Real-Time Computing
The new CPU is a RISC-V core for real-time processing. To reduce die size (cost) and help ensure determinism, it will be an in-order, scalar design. To enhance throughput, it supports fast context switching by adapting multithread technology. Whereas multithread CPUs choose threads round robin or to fill unused execution slots, the new MIPS design will switch contexts when triggered by an external event.
Eliminating overhead, this approach should make context switching instantaneous. This will improve real-time response rates, increase useful-work throughput, and raise power efficiency. Systems frequently changing contexts will see the biggest gains, and MIPS touts performance on sub-10 microsecond loops.
The new CPU will also implement special functions to accelerate computations associated with control applications. MIPS has withheld details, but we expect these to include the Cordic algorithm. Hardware implementations of functions can increase throughput and reduce power compared to software-based approaches.
Delivering MCU Silicon
To reduce customers’ time to develop a microcontroller (MCU), MIPS will deliver the new CPU in the M8500 subsystem. We expect the subsystem will integrate peripheral functions such as a memory controller, timers, an interrupt controller, an encryption accelerator, and platform security features. Consistent with the company’s safety focus, the M8500 will support ASIL-D and other safety standards.
The initial M8500 subsystem delivery will be a simulator based on the Synopsys ImperasFPM reference model integrated into an extension for the Visual Studio Code development environment called Atlas Explorer. Available before 4Q25, Atlas Explorer helps customers get an early start developing software and planning how to integrate the M8500 into their design.
Later this year, MIPS plans to offer an FPGA-based development board. Fabbed in a 22 nm FD-SOI process, a hardened implementation comes next year. MIPS aims not to become an MCU supplier but to offer only reference silicon. The company seeks to give OEMs that sometimes commission ASICs a simpler way to create a unique MCU with proprietary function blocks, expanding its market beyond historical licensees possessing the capability to incorporate a basic core into an SoC.
Bottom Line
Licensing RISC-V cores is a tough business. Many suppliers crowd the market, and free open-source versions are available. Demand for high-value, high-performance RISC-V application CPUs has yet to materialize, restricting RISC-V to deeply embedded and control-processing niches.
Adapting to this reality, MIPS is leaning into the control market, developing CPUs optimized for real-time applications, adding safety capabilities, and complementing them with AI acceleration. By developing a chip, the company seeks not to forward integrate but to enable more OEM customers to backward integrate and make bespoke MCUs. MIPS already claims a design win with an automotive customer, expecting its chip to enter production in 2027. It’s a good start for the company with a long and rocky history, but to retain momentum, the company must deliver the S8200 and M8500 on the timeline it has set.