In October, Xsight Labs introduced a top-of-rack switch IC and an accompanying DPU, the E1. Expected to sample in a few months, the E1 is both a standard Linux host and a flexible data-plane processor. Few startups are chasing the data-center-switch market, and—following a burst of activity in the 2010s—even fewer are developing DPUs. Defined narrowly, a DPU is a niche technology, but the E1’s design has more potential than past smart-NIC chips.
Sidebar: Defining Terms
We’ve previously applied data-processing unit (DPU) to processors principally intended to be the main chip on a smart network interface card (NIC). That’s not to say that they couldn’t play different roles or that other ICs couldn’t be a smart NIC’s main chip, only that DPUs targeted these designs.
A defining DPU feature is a degree of data-plane programmability. In addition to specialized networking engines, most incorporated general-purpose cores (CPUs) for upper-layer network functions. Thus, they differed from network processors (NPUs), which focused on OSI Layers Two and Three for routing applications. At the same time, DPUs typically differed from multicore communication processors in that the general-purpose CPUs in most designs were adjuncts, not the principal function block. Marvell, however, disagrees with our previous definition and labels its Octeon multicore processors as DPUs. We now agree and put processors targeting smart NICs and multicore communication processors in the DPU category.
Blending Computing and Networking
Although it fits the original DPU definition, the Xsight E1 also qualifies as a comm processor. It integrates 64 Arm Neoverse N2 (Perseus) CPUs, which are the infrastructure version of the Cortex-A710 (Matterhorn) and more power- and area-optimized than the performance-focused Neoverse V and Cortex-X cores. Standard Arm CPUs, the N2 cores are speedy and able to run general code, including hosting Linux distributions such as Debian and the networking-focused Sonic.
Importantly, they also reside in the data plane. In Xsight’s design, traffic between PCI and Ethernet ports traverses the CPU cluster—an impressive feat considering the E1’s 800 Gbps aggregate data rate. To achieve this rate, numerous inline engines offload parsing, classification, encryption, and other functions. Linux drivers enable code to call other engines to execute networking primitives, further offloading the cores.
Although Xsight has been able to combine computing-style programming with wire-rate networking, it comes at the cost of additional power compared with implementing more functions in specialized hardware. The company is betting that their approach’s flexibility will allow the E1 to address new features that a more rigid design couldn’t, a key selling point for data-center operators continually updating their networks to handle additional workloads.
In the short term, an immediate E1 application will be as a smart-NIC chip. In the context of a data center deploying the company’s X2 switch chips, the E1 is also essentially a fabric adapter. In that role, one function is buffering packets to allow the X2 and host processor to do what they do best: switching and computing. Looking forward, a more powerful E1 successor could handle faster data rates and, in networking and storage appliances, also take on tasks that now require a host processor.
Bottom Line
The Xsight E1 complements the X2, handling tasks at the host side in a big data-center network. The E1’s unusual combination of data-plane performance and software-based flexibility promises to future-proof data-center networks. These same features position the E1 to address designs handled by multicore communication processors, expanding the markets it can serve.
Links and Other
- Xsight E1 product page
- Bob Wheeler’s E1 white paper
Image: E1 software stack. Credit: Xsight Labs