• Arm Neoverse V3 and N3 Turn Up the Heat on X86

    Arm Neoverse CSS high-level block diagram showing blocks inside and outside the CSS forming a chip

    Arm has refreshed its entire infrastructure-CPU line, delivering new Neoverse V3, N3, and E3 cores. A rung up the integration ladder, the company also offers compute subsystems (CSS) that combine these CPUs, a mesh network, cache, and interfaces to facilitate customers’ SoC and chiplet designs. Arm reports V3 and N3 are typically about 13% and… continue reading


  • Plug: Get the Definitive 2024 RISC-V Report

    RISC-V logo

    The SHD Group has developed a detailed RISC-V report covering design starts by application, unit volume projections by market, and projections through 2030. Visit SHD’s website to receive a complementary version. For the full version, contact us here at XPU. We’ll relay your interest, and you’ll help support this site. continue reading


  • Sam Altman Proposes World’s Largest Cash Incinerator

    hand holding a burning 100 dollar bill

    In a spasm of incisive journalism, we’re reporting that various news sites are reporting that the Wall Street Journal has reported that Sam Altman wants several trillion dollars from Arab sovereign-wealth funds to fab and deploy AI chips, calling the project GlobalFoundries 2: AI Boogaloo. Shine bright, Sam. continue reading


  • AMD Ryzen Gets On Board With Xilinx Versal

    Picture of AMD Embedded Plus board from Sapphire

    Two years after completing its Xilinx acquisition, AMD has released a design combining an AMD-heritage processor with a Xilinx-heritage FPGA. The new AMD Embedded+ is a board, not a chip, however. It targets PC-like systems for industrial, medical, and other embedded applications. Taking over Xilinx, with its broad customer base, should help AMD expand its… continue reading


  • You Would Think There’s a Single Optimal Heterogenous Multicore Configuration for Power, Performance, or Area

    photo of three applie cores, one large and two small

    AMD’s blend of Zen 4 and Zen 4c cores in Phoenix 2 seems optimal, but the variety of heterogeneous multicore configurations in the wild suggests there’s no consensus optimum. continue reading


  • Why License Verilog When You Can Use Excel?

    Microsoft Excel logo

    Some guy made a gate-level CPU design in Excel. I’m only disappointed the compiler is in Python instead of VBA. continue reading



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